Technical and scientific leadership in information systems and software design.
Temporal logic processing, property verification methodology, reasoning, solver task composition. Strong expertise in formal technology.
Custom compilers. Data & algorithm optimization. Digital & analog circuit design. GUI/Graphics
System Verilog, Murphi
Strong analytical skills
Creative approach to task solving
Ability to work with highly integrated environment
Mentoring engineers in research and development
Willing to travel, advertise and communicate
Power Analysis & Optimization of novel Vector Instruction Pointer (VIP) microprocessor architecture|
|Strategic CAD research||Formal tools for software testing|
Proposed and implemented a set of optimizations for Direct Automated Random software Testing (DART) including Re-alternation Limiting strategy that enabled a breakthrough in bug detection rate
Correct by construction layout generation
A pioneering automated flow for poly silicon layout design rule compliance based on SAT solvers.
Formal equivalence check against an abstract model
Proposed and proven an effective method for formal equivalence verification against High Level Model (HLM), developed a compiler to enable the flow.
|SW Tools development||Formal Property verification in HW design|
Property Compiler – an application for logic design formal verification - one of the key contributors.
Implemented System Verilog Assertions (SVA) standard support in Formal Verification flows. Developed SVA Advisor - a WYSIWYG application facilitating scribing and understanding of SVA statements.
|Other||Presenter @ Intel SWPC conferences: 2012; 2010 (Best Demo award)|
Worked on VLSI/Compass/Avant!/Synopsys CAD tools development and support as a part of MCST outsourcing projects
|CAD/CAE tools for logic
composing, editing layouts,
rule checking etc.– outsourcing projects
Graphical interfaces & visualization for CAD/CAE
Algorithms on networks
CAD framework (cell caching, logistics etc)
Developed an universal text/GUI configuration system for CAD components (“Option manager”)
Installation & license management applications, remote interfaces etc.
Technical documentation make-up
Developed an internal synthesis system for implementing parts of Elbrus computer logic in field programmed gate arrays (Altera FPGA)
Electronic design & electronic equipment and production:car electronics, show lighting controllers
Conditional jump Re-alternation Limiting based speed-up of Directed Automated program testing.// Micro- and nanoelectronic system design problems conference, 2012, Moscow
High Level Model based Verification of Digital Circuit Behaviour.// Micro- and nanoelectronic system design problems conference, 2010, Moscow
Realization of solver based techniques for dynamic software verification. Microsoft Summer School in Software Engineering and Verification, Moscow, Russia, on July 17–27, 2011
“Property Verification” as a part of “Math Basics of CAD“ course for Intel interns, Moscow Institute for Physics & Technology (Technical University) (MIPT)
Information Retrieval, particularly, search through Social networks
“Correct by construction” software and hardware development methods and tools
Andreas Scherbakov — firstname.lastname@example.org